Marvell has brought out the industry’s first 260-lane PCIe 6.0 switch.
The Structera S PCIe 60260 switch is expected to begin sampling to customers in calendar Q3 2026.
Engineering test samples of the switch are available now.
Leveraging interconnect technology obtained through its recent acquisition of XConn Technologies, the switch extends the Marvell end-to-end PCIe portfolio.
As AI servers integrate increasing numbers of GPUs and accelerators, PCIe scale-up fabrics have become critical to maximizing compute density and resource utilization.
Traditional switches require multiple devices to achieve scale, resulting in increased power, latency, board complexity and total cost of ownership. The Marvell Structera S 260-lane PCIe 6.0 switch eliminates the need for multiple smaller switches, enabling higher density, lower latency and improved system efficiency.
The addition of XConn Technologies PCIe switches to the Marvell PCIe portfolio augments the Marvell Alaska P PCIe retimer product line, which scales connections between AI accelerators, GPUs, XPUs, CPUs, SSDs, CXL devices and other components. Alaska P PCIe retimers enable low-power, high-speed and low-latency connectivity that scales within servers and clusters to power accelerated AI data center infrastructure.
Combining the new Structera S PCIe switch with the Alaska P PCIe retimer solution, Marvell offers a comprehensive, end-to-end portfolio of PCIe solutions that provide hyperscalers and data center customers with a flexible interconnect platform to meet their individual configuration requirements. The combined solution unlocks the physical limitations of high-speed PCIe I/O, enabling active electrical cable (AEC) partners to extend PCIe 6.0 cable reach up to seven meters and active optical cable (AOC) partners to extend reach beyond seven meters.
In addition, Structera S PCIe switches are drop-in, pin-compatible with new Marvell Structera S CXL 3.0 switch offerings allowing customers to design a single hardware platform that supports both PCIe and CXL applications, while reducing development costs, shortening design cycles and maximizing design flexibility.
