The core adds to Fraunhofer’s portfolio of Time-Sensitive Networking (TSN) IP cores.
It is designed for demanding applications that require maximum bandwidth, precise time synchronisation and reliable data transmission with exact timing.
Compared to the previous 1G TSN IP cores, the new 10G TSN EP IP core enables a 10-fold increase in data throughput, reaching up to 10 Gbit/s, while maintaining consistent, deterministic behaviour throughout the network.
The new core is technically based on a robust, hardware-accelerated implementation of time synchronisation, according to IEEE 802.1AS-2020 (gPTP).
This allows the core to achieve synchronisation accuracies of less than 10 nanoseconds in Ethernet networks and ensures stable time bases, even at very high data rates. It supports key TSN standards, including IEEE 802.1Qav for audio/video traffic shaping, IEEE 802.1Qbv for time-controlled scheduling, IEEE 802.1Qci for per-stream policing and IEEE 802.1CB (FRER) for redundant, fault-tolerant transmissions.
To facilitate rapid implementation, Fraunhofer IPMS provides Linux driver packages and reference implementations. The latter cover native XGMII interfaces, as well as common 10G interfaces, such as 10G-BASE-R, SFI, and XFI.
These interfaces are found on AMD Xilinx FPGAs, for example. The 10G TSN-EP IP core is designed for a wide range of proven FPGA and asic target platforms, facilitating rapid integration into customer-specific designs.
