Asics

Globalfoundries says it has demonstrated 56Gbit/s SerDes performance in silicon on the semiconductor foundry’s 14nm FinFET process. This makes it able to fabricate Asics which will meet the emerging 50Gbit/s industry standards such as OIF CEI-56G-LR and IEEE 802.3cd. The SerDes core, designated FX-14, supports both PAM4 and NRZ signaling, with the capability to equalise over 35dB of insertion loss. “The explosive growth ...

Delta Microelectronics, the Denmark-based Asic services firm, is now partnering with Solution in Silicon in the UK. With an interest in medical, communications and security markets the partnership will expand Delta’s supply chain services including wafer procurement and probing, packaging, component testing, storage and IC distribution in the UK. Gert Jørgensen, Delta’s vice-president of sales and marketing, says the firm is seeing increased demand for its ...

Intersil announces high power digital multi-phase controllers equipped with AVSBus (adaptive voltage scaling bus), claiming them to be the first that communicate using the standard.

Imagination Technologies has announced the first of its Whisper Series5 radio baseband processors, which it calls radio processing units (RPUs). Available as intellectual property for integration into SoCs, there are versions for 802.11n Wi-Fi, Bluetooth Smart, or both. The cores are designed for low power consumption, and applications in wearables, IoT, and other connected devices are foreseen. “Repurposing mobile or ...

LSI Logic has added to its RapidChip structured Asic family new design options for high speed serial applications

Austriamicrosystems offers low power EEPROM blocks for its 0.35µm mixed signal Asics

AMI Semiconductor has moved its “lower entry cost” Asic platform to a 0.15µm process

Cambridge Consultants has a IDE for structured or platform Asic design.

High speed physical layer interface to QDR-2 SRAM memory

LSI Logic has introduced its first physical layer DDR-2 memory interface to support 333MHz/667Mbit/s data speeds.