Nios II core makes critical mass with Asic developers

Altera says it is making the move because the core has reached critical mass in the industry.
“It’s the most widely used soft CPU for FPGAs,” Chris Balough, director of software and embedded marketing, told EW.

“All 20 of the top 20 OEMs, tens of thousands of engineering users, and 40 per cent of Altera’s FPGA designers have used it. Until now they have been confined to using it on Altera’s silicon.”

As from Q1 2008, they will be able to use it on anyone’s silicon, so long as it is not Xilinx, Actel, Lattice, QuickLogic, MathStar or any other FPGA vendor’s silicon.

SoC, Asic and ASSP designers will be able to get their hands on Nios via the Synopsys DesignWare Star IP Program.

Synopsys said it will provide a configurable, fully synthesisable, version of the Nios II processor core optimised for Asic implementation. After that, the choice of foundry and process geometry is up to the user.

Asked if Altera will make any money from the move, Balough’s answers became opaque. He would not say whether Altera will get a license fee or a royalty from people who use a Nios core provided by Synopsys. For Synopsys there will a fee payable by users of Nios. “Customers have driven this,” said Balough, “it gives Nios more space to breathe.”

Synopsys was chosen to make the core available, because, said Balough: “Synopsys is the second largest IP provider after ARM.”