The chip has a novel memory subsystem designed to overcome bandwidth bottlenecks and mitigate supply constraints tied to high-end memory.
By optimising data flow and memory access, Semidynamics enables large-scale AI inference models to run more efficiently—supporting high-concurrency applications while reducing total cost of ownership.
Semidynamics will offer a vertically integrated stack—chips, boards, and racks—targeting leading-edge, multi-accelerator AI platforms.
“Our 3nm tape-out is a vital technical validation as we execute a rigorous multi-stage roadmap toward delivering product-ready silicon and rack-scale systems,” says CEO Roger Espasa.
