Imec’s record-breaking ADC

Imec has unveiled a 7‑bit, 175GS/s ADC that combines a record-small footprint (250 x 250µm²) and low conversion energy with one of the fastest sampling speeds ever reported.

As such, the ADC meets the rapidly increasing throughput and processing demands of AI- and cloud-driven datacentres, without the area and power explosion typically seen at ultra-high sampling rates.

Driven by AI and cloud applications, data centers’ optical communication networks need constant upgrades to handle ever-higher throughputs and processing demands.


Imec’s record-breaking ADC

But as sampling rates climb beyond 100GS/s, the underlying components – such as wireline ADCs, essential in optical transceivers – tend to grow in size, requiring longer interconnects, and introducing parasitics and energy loss.


At the 2024 ISSCC, imec tackled this challenge with a breakthrough: a massively time-interleaved slope-ADC architecture at least twice as compact as conventional designs and featuring state-of-the-art power efficiency.

Building on that approach, imec now takes the next step with the introduction of a record-small ADC that ensures precise signal conversion and wide bandwidth at ultra-high sampling rates.

“Our 7-bit, 175GS/s ADC – implemented in 5nm FinFET technology – pairs a record-small core area of 250 x 250µm2, and low conversion energy (2.2 pJ per sample), with a sampling speed that ranks among the fastest ever reported. This makes it a compelling solution for upscaling digital‑intensive wireline interconnects, where every square micron and milliwatt count,” says Imec’s Peter Ossieur.

Two patented innovations make this possible. First, a novel linearization approach – shaping the slope signal – corrects distortions. Second, switched input buffers efficiently feed the ADC’s 2,048-channel time-interleaved array, minimizing electrical load and enabling ultra-fast sampling without compromising signal integrity

Building on the ADC presented at this year’s ISSCC, imec is now developing a 3nm follow‑on design and exploring 14 Ångstrom designs, exploring how such advanced nodes can be leveraged for high-performance wireline data converter designs.

Peter Ossieur: “Imec has a long-standing track record in developing high-speed integrated circuits for communication applications. One of our key research tracks focuses on optical transceivers (and their building blocks) that can keep pace with the rapidly increasing data rates in wireline systems. In this context, our ADCs represent a crucial step toward a new generation of compact, low-power converters for future wireline applications, pushing beyond the performance limits of SAR-based ADC architectures at ultra-high speeds. To accelerate this effort, we warmly invite partners – including fabless companies developing wireline connectivity building blocks – to join our ADC and DAC research programs, with licensing options available to access imec’s underlying IP portfolio.”

See all our Imec content.

David Manners

David Manners

David Manners has more than forty-years experience writing about the electronics industry, its major trends and leading players. As well as writing business, components and research news, he is the author of the site's most popular blog, Mannerisms. This features series of posts such as Fables, Markets, Shenanigans, and Memory Lanes, across a wide range of topics.

Leave a Reply

Your email address will not be published. Required fields are marked *

*