SOI finfets will scale to 11nm, according to Professor Asen Asenov, which means they will be useful for at least three generations of process technology.
Process R&D
Europe needs fab and 450mm involvement, says Andreas Wild
Europe is needy. It needs a fab, it needs to compete in the 450mm transition, and it needs to fill gaps in the European technology value chain, Andreas Wild, executive director of Eniac, the EC R&D initiative, told the recent European Nanoelectronics Forum in Dublin.
ARM and TSMC moving fast to 20nm
ARM and TSMC are moving fast to get Cortex A-15 out on a 20nm process. A chip has already been taped out and an ARM process team has been set up in Taiwan to handle the transition.
Euro Nanoelectronics Forum: The Japanese are nowhere near us on EUV, says ASML
"EUV has arrived at customer sites and is here to stay," Anton van Dijsseldonk of ASML, told the European Nanoelectronics Forum 2011 in Dublin this morning. "EUV has arrived at customer sites and is here to stay," Anton van Dijsseldonk of ASML, told the European Nanoelectronics Forum 2011 in Dublin this morning.
IBM and ARM lead way for very low power SOI chips
A design feature of FD-SOI is its potential to operate complete IP cores or full chips at very low supply voltages down to 0.5-0.6V
450mm could cost $40bn, says CEA-LETI
The 450mm wafer transition could cost $40bn says CEA-LET's Michel Brillouet. SEMI puts the cost at $25-40bn with much of it centred at the Global 450 Consortium (G450C).
Imec says high speed SiGe:C devices are ready for volume
"Compared to III-V HBT devices, SiGe:C HBTs combine high-density and low-cost integration, making them suitable for consumer applications," said Imec
Imec and ASML deal moves EUV lithography closer
Imec's EUV lithography work will use the production-ready EUV litho system NXE:3300B, the successor of ASML’s NXE:3100 preproduction tool that has been installed at imec in Spring 2011
Globalfoundries produces first 28nm MIPS multi-processor
MIPS provided the RTL based on its MIPS32 1074Kf embedded multi-processor technology and eSilicon performed the synthesis and timing-driven layout of a three microprocessor cluster running at 1GHz
IEF2011:Scaling no longer delivering cost reduction, says Mentor
Scaling is no longer delivering sufficient cost reduction and there’s not much hope of getting back to traditional Moore’s Law cost decreases purely by process technology advances, according to Joe Sawicki, vp and gm of the design to silicon division at Mentor Graphics speaking to the IEF 2011 meeting in Seville this morning.
