DAC

A single structure built in the metal layers of an IC can implement both machine learning and analogue AI inferencing, according to a French team led by Grenoble lab CEA-Leti – and the CMOS below can also be used for processing. Made between two metal interconnect layers, the structure has four layers: TiN at the bottom, Si-doped HfO2, a Ti ...

There is a general consensus and belief that chiplets are the future, said Abhijeet Chakraborty, VP engineering, Synopsys. There are, however, no illusions about some of the challenges or obstacles that have to be addressed, he added. The first of these is interoperability and standards. Access to chiplets is essential to design any complex, large system, Chakraborty told Electronics Weekly ...

A new working group has been announced to establish cross-industry collaboration to improve the interoperability of product and environment simulation, models, and components using existing and new open standards. Accellera Systems Initiative announced the Federated Simulation Standard (FSS) working group (WG). The charter of the new working group is chaired by NXP’s Martin Barnasconi,with Qualcomm’s Mark Burton as vice chair. ...

How does the (US) Chips Act affect innovation? This question was posed at DAC and the expert panel agreed that there is no lack of engineering talent but how to corral it to the right areas is proving more complex. Saverio Fazzari, senior lead engineer at management consultancy Booz Allen Hamilton. Workforce development, expressed his hopes for the cash injections. ...

Keysight has combined it Electromagnetic Simulator with Synopsys’ AI-powered RF design migration flow for an integrated design flow to migrate from TSMC’s N6RF+ to N4P process technology. The migration workflow builds on the foundry’s Analog Design Migration (ADM) methodology to streamline the redesign of passive devices and design components to the advanced RF process rules. The collaborative migration workflow leverages ...

For physical AI at the edge, MIPS has introduced the Atlas Explorer portfolio. The company explained that it allows designers cycle-accurate repeatability of their workload onto a MIPS processor. It provides access to platform IP ahead of silicon availability for evaluation to enable pre-production RTL and for teams to develop optimised hardware and concepts such as digital twins to gain ...

DAC 2025: There was a lot of talk about AI at this year’s DAC but one of the most significant was that Siemens Digital Industries Software has added generative and agentic AI capabilities across its EDA portfolio. The EDA AI system applies across all semiconductor and PCB design suites, including Questra, Tessent, Xpedition, Veloce, Catapult, Calibre, Aprisa and Solido.  “It ...

This week we're talking about 2.5D and 3D IC design, the robotaxi market, a rush of accelerometers, and sampling broadband satcom signals for navigation purposes...

Designers looking to optimise PPA (power, performance, area) are finding that optimisation engines can render original programmatic timing constraints unusable in their original form. At DAC 2025, Ausdia introduced Timevision OneSource which automatically generates a new version of block-level constraints after optimisation engines have worked on hierarchies, duplicate elements and performed advanced transformation. Such optimisations can save two weeks of ...

DAC moves to Long Beach, southern California for 2026. The exhibition and conference covers chips to systems with education, exhibits, training and networking opportunities for designers, researchers, tool developers and vendors. It is of interest to system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives, and researchers and academicians from leading universities. The ...