The Cadence memory model for xSPI enables use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI non-volatile memory (NVM).
Code-intensive wireless stacks and artificial intelligence processing necessitate high transfer rates and low latency for flash memory devices in IoT systems.
Expanding the traditional four I/Os (quad SPI) to eight I/Os (octal SPI) with the xSPI serial synchronous protocol increases the serial NOR flash throughput.
David Peña, verification IP product management director, system & verification group at Cadence said “The availability of the memory model for Adesto’s EcoXiP and host controller design IP for xSPI devices enables joint customers to quickly and easily adopt xSPI while developing their products.”
Adesto says its EcoXiP NVM eliminates the need for expensive on-chip embedded flash in a broad range of emerging IoT applications.
“Moving intelligence to the edge can provide significant advantages, but heavier local processing means that architects must revisit their system’s memory architecture,” says Gideon Intrater, Adesto’s CTO.
“xSPI makes it easier for system designers to reap the benefits of octal devices like EcoXiP for smarter, more efficient and user-friendly designs.”
The Cadence memory model for xSPI is part of the Cadence verification suite and is optimized for Xcelium parallel logic simulation, along with supported third-party simulators.
