BWM has picked Green Hills’ software for control units in its iX all-electric vehicle. Integrity real-time operating system is used in the digital instrument cluster, head-up display, driver camera system, surround view and parking assistant. Software developers, according to Green Hills, used its Multi integrated development environment, and ASIL-qualified compilers and run-time libraries for both Integrity and AutoSar Classic operating ...
Verification and stimulus specialist, Breker Verification Systems, has taken its Cache Coherency TrekApp as the basis for the System Coherency Synthesis TrekApp, which it introduced at DAC58 in San Francisco. The tool uses abstract models of common and novel algorithms to automatically generate high coverage coherency tests for complex, multi-agent system platforms based on coverage directives. The TrekApp can be configured ...
At DAC, French embedded FPGA (eFPGA) supplier, Menta, introduced what it claims is the first eFPGA soft IP. It enables designers to perform closure directly at the top level. This is significant for AI, as well as space and defence projects, which rely on low latency, explained Yoan Dupret, Menta’s managing director and CEO. Since 2013, Menta’s technology has ...
To gain at least an 18 month advantage in getting a product to market, Verific Design Automation builds SystemVerilog, UPF and VHDL parser platforms which accelerates the production cycle because the RTL front end is immediately accepted by the semiconductor industry, says the company. It offers parsers, analysers and elaborators for SystemVerilog IEEE 1800-2005 / 2009 / 2012 / 2017, ...
Joe Sawicki , executive vice president, IC EDA at Siemens, challenged the mutterings that Moore’s law has run its course, and said the semiconductor industry was blighted with pessimism. At this year’s DAC (Design Automation Conference) he set about looking at the figures in a new light. “There have been morose expectations and miserable prognostics, for like 20 years,” he reasoned, ...
Sheffield memory design house SureCore is offering intellectual property to cut register file power consumption. Branded MiniMiser, its architecture is based on a customised storage element – rather than on the foundry bit cell – and exploits the company’s SRAM power saving techniques. Multi-port and high-performance variants can be generated. “MiniMiser gives developers a new way of optimising the power envelope ...
SiFive has created what “is expected to be the fastest licensable RISC-V processor IP core in the market”, when it emerges in 2022. Building on the earlier Performance P550 processor, company engineering estimates are that it will have 40% more performance per clock cycle – to 11+SPECInt2006/GHz – and it has architecture enhancements improve maximum clock frequency – together adding ...
The role of EDA tools to automate manipulating, storing and exchanging data for functional safety systems was in the spotlight at DAC, as engineers wrestle with ways to improve interoperability, traceability and automation. The Accellera Functional Safety Working Group was created in December in 2019 and is dedicated to standardise across system, module, component and IP levels to define an ...
Following its created in April this year, the Open Source FPGA Foundation was at DAC (Design Automation Conference) to advocate for innovation with open source tools and wrestle control from what has been a largely unchanged FPGA space for 30 years. The fledging non-profit foundation has over 20 members from academia and more than 1,000 individual members worldwide, said CEO, ...
Imagination Technologies has announced Risc-V CPU intellectual property for SoC companies. Branded Catapult, it is a “product line designed from the ground-up for next-generation heterogeneous compute needs,” according to Imagination. “Leveraging Imagination’s 20 years of experience in delivering complex IP solutions, Catapult CPUs can be configured for performance, efficiency or balanced profiles.” There will be four families: dynamic microcontrollers real-time ...
