Mentor Graphics is bringing a C synthesis product to market that was previously available to select customers. Catapult C takes standard C or C++, with no extra instructions, classes or timing information, and produces Verilog or VHDL code for either an Asic or FPGA. “The source is purely functional, so the designer doesn’t care about the architecture,” said Thomas Bollaert, ...
EDA and IP
EDA start-up secures $9m funding
Golden Gate focusing on EDA for low power chips
Synopsys revenue up slightly
EDA firm manages one per cent growth over last year's quarter
EDA tool tracks power and noise into package
Start-up firm addresses power management issues
Synopsys unwraps Galaxy design platform
Improvements to whole range of chip design tools promised
ARM unveils multi-processing and DSP cores
Fruits of collaboration with NEC and acquisition of Adelante
Fister leaves Intel for Cadence
Bingham named chairman of the Cadence board
MoSys blames loss on missed acquisition
Firm says cancelled buyout by Synopsys to blame for quarterly loss
China rule change raises IP theft concerns
The threat from China’s theft of intellectual property is expected to grow worse over the next seven months, as the country begins lifting restrictions on what indigenous companies can export. Meetings were under way this week in Beijing and Washington, D.C., between industry groups and government officials in both countries to develop a plan to combat the problem. But executives ...
Magma adds power optimisation
Power optimisation and management has been added to Magma Design Automation's chip design software.
