Ambitious plan to extend firm's product roadmap into chip level planning and implementation
EDA and IP
Initiative cuts 90nm power by 40%
Industry collaboration makes significant power savings on 90 nanometre ARM processor design
Network-on-chip tools replace bus
Arteris unveils tools that implement network-on-chip technology to replace conventional bus structures
End of point tools, says de Geus
The chairman and chief executive of Synopsys says the big firms are pushing designers into using complete design flows
DATE: Optimising power in IC design
Power – too much of it – is a recurring theme at this year’s DATE show in Munich
DATE: IBM talks chips in EU
A collaborative effort between IBM, several European companies and universities, and the European Union has paid off, producing...
DATE: CoWare tunes radio with IMEC
EDA firm CoWare has been boosted by signing a deal for its tools to link with IMEC’s software defined radio programme
IP is not peripheral for VaST
VaST Systems is enhancing its tools with a peripheral IP builder at this year's DATE conference
Novas debugs multi-processor
Debug specialist Novas has a tool for debugging complex multi-processor SoCs
ARM, Synopsys get dynamic
ARM and Synopsys have partnered to create a reference flow for designers using dynamic voltage control
