EDA and IP

Battle looms with Cadence and Verisity on one side facing Synopsys and Mentor Graphics on the other

Issues around design for manufacturability gather pace

Conference sees 19 different companies flying the ESL banner

Design for manufacture, power and standards are key issues, according to top three CEOs

Standard for how IP is implemented in EDA tools is released by the Spirit Consortium

Intel's Pat Gelsinger says the progression of Moore's Law will fundamentally change the tools required to design chips

Multiple die in a package seen as solution to rising Asic costs

Programmable firm hopes to increase demand for hard wired versions of its FPGAs

Growth from increasing number of cores, a shortage of engineering capacity and increasing importance of FPGAs

Router optimises wire by wire