This initiative will focus on design automation and chip architecture research.
The consortium will benefit from the NanoIC pilot line, turning academic insights into industry-focused innovations.
Similar consortia will be set up around advanced materials and alternative compute systems.
CMOS 2.0 refers to a new paradigm, introduced by imec, that expands the chipmaking toolbox beyond traditional transistor scaling and its associated scaling challenges.
CMOS 2.0 allows for more design flexibility by exploiting fine-grain wafer stacking technology to improve on-chip connectivity and offer higher technology heterogeneity to the system.
It will result in tailored chips comprising multiple 3D-stacked layers that fulfil smartly partitioned functions. In that way, CMOS 2.0 will provide advanced, versatile 3D stacked platforms that push the boundaries of compute performance.
Introducing this new paradigm will have profound implications on how computing architectures are designed and optimised for future workloads and applications.
CMOS 2.0 is a key differentiator for the realization of next-generation energy efficient compute systems and is expected to impact a wide variety of applications from general purpose processors to High Performance AI Computing systems and even further for embedded AI applications at the edge.
This strategically important research requires cross-pollination between different areas of the ecosystem. Within imec’s CMOS 2.0-consortium, 26 PhDs will be funded. The PhD students will stay at their home university, embedded in their research group, allowing them to tap into complementary fields of expertise and stimulate cross-fertilization.
The participating universities and imec will jointly develop the necessary know-how that lays down the foundation of the next generation CMOS technology platforms and their associated compute architectures. Moreover, the collaboration will support workforce and skill development in Europe to meet current and future industry needs.
Sahar Sahhaf, Director Academic Partnership Development: “The attraction for the concept of CMOS2.0 is clear, but the obstacles are equally substantial. Leveraging the benefits in both connectivity and heterogeneous integration enabled by 3D wafer stacking will reshape every stage of design and chip architecture. It requires convergence of expertise, close collaboration, and coordination.”
Mehdi Tahoori, Technical Director:” This university research consortium aims to infuse CMOS 2.0 technology to the entire design stack, from Electronic Design Automation (EDA) all the way to system architecture.”
Of particular importance is the presence of the NanoIC pilot line. PhD students can gain early exposure to next-generation semiconductor logic, memory and 3D technologies through process design kits (PDKs), which will enable them to develop system‑level thinking; which is typically only encountered much later in a research or industrial career.
As such, it bridges the gap from academia to industry, facilitating a rapid transfer of knowledge and advanced technology from research labs to the market, thus strengthening Europe’s industry.
The CMOS 2.0 university consortium consists of following universities:
- National Technical University of Athens
- Delft University of Technology
- École Polytechnique Fédérale de Lausanne (EPFL)
- Eidgenössische Technische Hochschule Zürich
- Karlsruhe Institute of Technology
- Katholieke Universiteit Leuven
- KTH Royal Institute of Technology
- LIRMM, University of Montpellier, CNRS
- Politecnico di Torino
- Sabancı University
- Universidad Complutense de Madrid
- Universiteit Gent
- Université libre de Bruxelles
- University of Thessaly
