“The pace at which AI has permeated virtually every aspect of society has been nothing short of mind-blowing,” says CEO Van den hove, adding that it is far less predictable than transistor scaling.
“Let’s take large language models (LLMs) as an example,” he adds. “While they could still play a role in enabling future AI breakthroughs, they come with a significant limitation: they don’t truly learn – they are trained. I believe the next generations of AI – agentic AI, physical AI, and others – will be driven by machine learning approaches such as reinforcement learning, continual learning, and autotelic learning.
“These learning approaches will enable AI systems to build internal world models – rather than rely on pre-trained language models – and to adapt to new situations without forgetting what they’ve already mastered, much like humans do.”
Integrating such capabilities into AI systems will inevitably reshape the underlying chip architectures, even if the exact implications are not yet fully understood.
“It’s why we have established imec.AI-labs: a team that will connect emerging AI paradigms with our deep semiconductor know-how,” says Van den hove. “Building this lean, highly agile group of a few dozen experts – capable of moving fast and delivering meaningful impact – will be a major priority next year. It will be essential to cement imec as a leading force shaping AI’s long-term roadmap, and by extension, the hardware roadmap for sustainable compute systems.”
Advancing the underlying chip architectures remains a top imec priority for 2026. This ambition drives not only innovations in materials and (process) technologies, but also the continued refinement of classic design-technology co-optimisation and system-technology co-optimisation approaches, alongside the introduction of imec’s new cross-technology co-optimisation (XTCO) paradigm.
“A new era of grand chip scaling challenges has begun. XTCO is our answer to those challenges,” says CEO-elect Patrick Vandenameele, “next-generation AI systems are becoming increasingly complex. To meet their demanding memory, power, thermal, and reliability requirements, chips are evolving into heterogeneous assemblies of multiple technologies that continuously interact with – and influence – one another.
“The thing is: within this heterogeneity lies an enormous opportunity to optimise and scale across technologies. That is the essence of XTCO. It tackles the challenges that keep our system and fabless partners awake at night by introducing a disruptive, holistic approach to scaling – from compute density, memory capacity and bandwidth, and power delivery and management, to thermal performance, and reliability. We believe meaningful progress can only be achieved by jointly optimising these dimensions.”
But doesn’t solving a bottleneck in one area risk shifting the limitation elsewhere?
“Absolutely,” Vandenameele acknowledges. “That’s precisely why cross-technology scaling requires constant iteration and dialogue across domains. It’s also why imec is uniquely positioned to lead this effort: our ecosystem brings together all relevant players – enabling the continuous, end-to-end collaboration essential for XTCO to succeed.
“But make no mistake: materials and (process) technology innovations, from introducing CFET devices architectures to taking the next steps in the CMOS2.0 roadmap – and bringing these innovations from lab to fab – will remain fundamental. This is where enablers such as High NA EUV, 3D integration technology, and photonics come into play.”
High NA EUV lithography – the next major leap in patterning, enabling sub-2nm chip fabrication – was developed at record pace in the joint ASML-imec High NA EUV Lithography Lab in Veldhoven, the Netherlands.
“Building trust in – and de-risking – new technologies is where imec has always played a critical role. Working closely with our partners, our mission is to mitigate risks and ensure a smooth path to adoption. That’s precisely what we have been doing at the Veldhoven lab,” says Van den hove.
“Established to accelerate High NA EUV’s commercial readiness, the lab has delivered extensive data and key breakthroughs – not just in single exposure, but also in patterning advanced logic and DRAM structures – demonstrating that the technology can fully support A10 nodes.
“From an infrastructure standpoint, 2026 is shaping up to be an exciting year for imec, with the next-generation High NA EUV scanner set to be installed on our Leuven campus,” says Van den hove. “Securing this scanner – along with a full suite of state-of-the-art ASML tools – and building the underlying expertise in Europe is a major achievement.”
Imec is “home to the world’s largest patterning ecosystem, with more than 60 partners,” ’says Van den hove, “everyone who matters in lithography and patterning is here.
“On the research side, our focus remains on helping customers unlock the full potential of High NA EUV – by integrating and testing it in commercial process flows and ensuring platform stability under real manufacturing conditions.
“At the same time, we will continue to push the limits of High NA EUV by exploring next-generation nodes – including logic A7 and A5, as well as DRAM 0a and DRAM 0b technology.
“By enabling ultrafast data exchange over short-reach 
and short-haul interconnects, photonics will form the backbone of large-scale, energy-efficient computing systems – essential for cloud computing and advanced AI workloads.”
Photonics is emerging as another cornerstone technology – notably when it comes to enabling next-generation computing.
By enabling ultrafast data exchange over short-reach and short-haul interconnects, it will form the backbone of large-scale, energy-efficient computing systems.
This is essential for cloud computing and advanced AI workloads, which generate massive data flows and demand ultra-high-speed, low-power optical links – both within and between datacentres.
“Our ambition is to evolve from being primarily an incubator to becoming a true venture accelerator,” says Vandenameele “On the one hand, this means taking imec-born ventures to a higher level of maturity – ensuring they are fully investment-ready and highly attractive to external investors.
“At the same time, it calls for deeper engagement with the international venture capital community, enabling us to bring the next generation of breakthrough technologies – whether originating from imec or sourced externally – successfully to market,” adds Vandenameele.
“Democratising access to cutting-edge semiconductor innovation is another powerful way to create impact,” continues Vandenameele. “By hosting the EU Chips Act’s NanoIC pilot line, for instance, we can give industry partners early access to beyond-2nm technology through a suite of advanced tools – such as early-stage process design kits (PDKs), design-pathfinding PDKs for next-generation chip architectures, and (3D) system-exploration PDKs that support prototyping of new components on commercially available foundry wafers.
“And finally, the transformation and expansion of our IC-Link activities fit perfectly into this strategy as well. By broadening IC-Link’s ASIC expertise, productising research IP, and extending the team’s reach into beyond-CMOS domains – think of our integrated silicon photonics (iSiPP) platform – we aim to make IC-Link a powerful bridge between world-class research and market-ready solutions,” concludes Vandenameele. “The goal: to unlock new opportunities for collaboration with fabless and system companies, as well as emerging players and startups.”
