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FPGA / PLD

The latest Electronics Weekly product news on FPGA (field-programmable gate array) and PLD (programmable logic device) devices to be (re)configured by a user after manufacturing.

System-on-module built around Intel’s Agilex 5 E FPGAs

IWave Agilex-5

iWave has announced system-on-modules built around Intel’s Agilex 5 E-series FPGAs, which have AI algorithm support. iW-RainboW-G58M measures 60 x 70mm, and is available with any of the 5 E-series ICs that come in Intel’s B32A (32x32mm) package. “Agilex 5 system-on-module is an ideal building block for equipment used in wireless communications, video, broadcast and industrial test and measurement sectors,” ...

Dev kit for space-qualified FPGAs with QML qualification

Microchip space fpga PolarFire dev kit

Microchip is aiming at satellite designers with a development kit built around its radiation tolerant RT PolarFire FPGAs, for which MIL-STD-883 Class B qualification has been gained and both Class Q and Class V qualification have been sought. October 2023 update: RT PolarFire FPGA’s are now QML (qualified manufacturers list) Class Q qualified, as designated by the US Defense Logistics ...

AMD to supply Spartan 6 FPGAs to 2030 at least

amd Spartan 6 fpga life extension

AMD will continue to supply Spartan 6 FPGAs until at least 2030, the company announced. The programmable ICs were introduced originally in 2009. “Spartan 6 devices, with high IO-to-logic ratios in small form-factor packaging, continue to be well suited for customers in industrial, medical, vision and automotive markets as well as other markets, like communications, where simple bridging is required,” ...

Intel shipping Agilex 7 FPGA with R-Tile

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Intel is shipping production-qualified volumes of the Intel Agilex 7 FPGA with  the R-Tile chiplet and  PCIe 5.0 and CXL capabilities. “Customers are leveraging R-Tile, with PCIe Gen 5 and CXL, to accelerate software and data analytics,” says Intel’s Shannon Poulin. R-Tile-equipped FPGAs make possible newer high-performance accelerators. FPGA accelerators can offload tasks from the host CPU, freeing up CPU ...

FD-SoI FPGAs get PCIe and LPDDR4 interfacing

Lattice Nexus fpga FD SoI transistor

Lattice Semiconductor is aiming at system control with a family of FPGAs that includes PCIe Gen 2 interfacing and embedded security. MachXO5T-NX, as they are called, are suited to “a set of control function designs for enterprise networking, machine vision and industrial IoT”, it said. They are built using the company’s FDSoI process (image right), which can dramatically reduce soft ...

32bit RISC-V certified ISO 26262 ASIL-D ready by TÜV SGS

Fraunhofer Albacopter

Fraunhofer Institute for Microelectronic Circuits and Systems IMS has had a version of its 32bit AIRisc RISC-V microcontroller intellectual property certified by by TÜV SGS to the ISO 26262 ASIL-D automotive safety standard. Called AIRisc-Safety, it can now be licensed from the organisation, which also offers customised versions for asic and FPGA integration. “Certification means that industrial customers directly receive a ...

FPGAs enable end-to-end security for 5G oran deployments

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Working with FPGAs allows architects and designers to deliver end-to-end security without sacrificing efficiency for telecom innovations, says Bob O’Donnell of TECHnalysis Research. Telecommunication vendors are in the middle of two technological revolutions that are driving the industry forward – the evolution of 5G networks and the transition to open radio access network (oran) architectures. Network architects are no longer ...

Digi-Key to host RVfpga Webinar on RISC-V architecture and implementation

RISC-V logo

Digi-Key has announced it will host a RVfpga webinar, in collaboration with Imagination Technologies, on the topic of understanding RISC-V architecture and implementation on an FPGA. Running on Wednesday 23 February, at 2 p.m. CST, it will be presented by Dr. Sarah Harris, associate professor of electrical and computer engineering at the University of Nevada, Las Vegas. Specifically, the webinar ...

Edge inference accelerator has an eye on Megapixel vision systems

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An edge inference accelerator developed by Flexlogix has a 4k MAC dynamic tensor processor array and is optimised for Mpixel image processing models in medical, surveillance and IoT applications. The InferX X1 edge inference accelerator is designed for processing real-time Mpixel vision workloads which requires high bandwidth support for deep learning models which operate with small batch sizes in real ...

eFPGA soft IP provides options for SoC and ASIC designs

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At DAC, French embedded FPGA (eFPGA) supplier, Menta, introduced what it claims is the first eFPGA soft IP. It  enables designers to perform closure directly at the top level. This is significant for AI, as well as space and defence projects, which rely on low latency, explained Yoan Dupret, Menta’s managing director and CEO.   Since 2013, Menta’s technology has ...