EnSilica and Codasip hook up on CHERI

EnSilica and Codasip have announced a strategic partnership to bring CHERI cybersecurity to automotive, critical national infrastructure, defence and aerospace applications

EnSilica, the ASIC specialist, and Codasip, a provider of functionally-safe and cyber-resilient RISC-V CPUs, will enable custom ASICs incorporating CHERI (Capability Hardware Enhanced RISC Instructions), Post-Quantum Cryptographic (PQC) acceleration, and advanced system-level security and safety features.

CHERI’s hardware security architecture is designed to mitigate memory safety vulnerabilities – one of the most significant sources of modern cyberattacks – and provides fine-grained compartmentalisation to increase software robustness and resilience.


EnSilica will use Codasip’s portfolio of 32-bit and 64-bit CHERI RISC-V processors as the foundation for developing customer-specific System-on-Chip (SoC) integrated circuits.


These secure platforms will integrate processing, PQC and classical encryption hardware, and tailored analogue and digital functionality to meet the precise requirements of the end application.

Ian Lankshear, CEO of EnSilica (pictured) said: EnSilica and Codasip hook up on CHERI“Cybersecurity has become a defining challenge for automotive, industrial and defence systems, with attacks growing in scale and sophistication. This partnership positions EnSilica at the forefront of delivering cyber-resilient chips that combine CHERI’s hardware-enforced memory safety with post-quantum cryptography. By building on Codasip’s advanced CHERI RISC-V processors, we can offer customers complete, application-specific ASIC solutions with security and functional safety designed in from the ground up. We are excited to work with Codasip to bring this next generation of trusted silicon to market.”

Dr Ron Black, CEO of Codasip added: “The partnership will help to unlock the full potential or our leading-edge 32-bit and 64-bit CHERI RISC-V CPUs. Developed in line with ISO 26262 functional safety and ISO 21434 cybersecurity standards, our processors come with a complete ecosystem including CHERI toolchain, CHERI Linux, and CHERI RTOSes. By combining these with EnSilica’s ASIC expertise, we can accelerate the adoption of CHERI-based security in mission-critical applications.”

 

David Manners

David Manners

David Manners has more than forty-years experience writing about the electronics industry, its major trends and leading players. As well as writing business, components and research news, he is the author of the site's most popular blog, Mannerisms. This features series of posts such as Fables, Markets, Shenanigans, and Memory Lanes, across a wide range of topics.

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